| 1 | # $Id$ |
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| 2 | |
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| 3 | PortSystem 1.0 |
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| 4 | name iverilog |
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| 5 | version 0.8.2 |
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| 6 | revision 1 |
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| 7 | categories science |
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| 8 | maintainers toby@opendarwin.org |
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| 9 | description Icarus Verilog |
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| 10 | long_description \ |
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| 11 | Icarus Verilog is a Verilog simulation and synthesis tool. It \ |
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| 12 | operates as a compiler, compiling source code writen in Verilog \ |
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| 13 | (IEEE-1364) into some target format. For batch simulation, the \ |
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| 14 | compiler can generate C++ code that is compiled and linked with \ |
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| 15 | a run time library (called \"vvm\") then executed as a command to \ |
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| 16 | run the simulation. For synthesis, the compiler generates netlists \ |
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| 17 | in the desired format. |
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| 18 | homepage http://www.icarus.com/eda/verilog/ |
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| 19 | platforms darwin |
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| 20 | |
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| 21 | master_sites ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ |
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| 22 | distname verilog-${version} |
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| 23 | checksums md5 41650504e4460508a0800008a2628e07 |
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| 24 | |
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| 25 | configure.args mandir=\\\${prefix}/share/man |
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| 26 | destroot.destdir prefix=${destroot}${prefix} |
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| 27 | |
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| 28 | test.run yes |
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| 29 | test.target check |
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