Ticket #48975: Portfile

File Portfile, 1.5 KB (added by yasu@…, 9 years ago)
Line 
1# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4
2# $Id$
3
4PortSystem          1.0
5PortGroup           python 1.0
6
7name                py-pyverilog
8version             0.9.6
9categories-append   devel
10license             Apache-2
11maintainers         prosou.nu:yasu
12supported_archs     noarch
13
14description         Python based hardware design processing toolkit for Verilog HDL
15long_description \
16    Pyverilog is an open-source hardware design processing toolkit for \
17    Verilog HDL. All source codes are written in Python. \
18    Pyverilog includes (1) code parser, (2) dataflow analyzer, \
19    (3) control-flow analyzer and (4) code generator.\
20    You can create your own design analyzer, code translator and \
21    code generator of Verilog HDL based on this toolkit.
22
23platforms           darwin
24
25homepage            https://github.com/PyHDI/Pyverilog
26master_sites        https://pypi.python.org/packages/source/p/pyverilog/
27distname            pyverilog-${version}
28
29checksums           md5 1221113d4904973da10d7e6653ac041a \
30    sha256 cdb36aee241e6b1f17101a4a9008fad9cd98cbad72b2d55f4718083439a3e90b \
31    rmd160 3cc3d75f0bfc82dfd99b793da01206ce0f7a4f51
32
33python.versions     27 33 34
34
35if {$subport ne $name} {
36    depends_lib     port:py${python.version}-setuptools
37    livecheck.type  none
38} else {
39    livecheck.type  regex
40    livecheck.url   https://pypi.python.org/pypi/pyverilog/
41    livecheck.regex {pyverilog ([0-9\.]+)}
42}