1 | # -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4 |
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2 | # $Id: Portfile 135995 2015-05-09 07:35:22Z ryandesign@macports.org $ |
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3 | |
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4 | PortSystem 1.0 |
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5 | |
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6 | name iverilog |
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7 | version 10.1.1 |
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8 | categories science |
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9 | license GPL-2+ |
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10 | platforms darwin |
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11 | maintainers paf@keeh.net |
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12 | |
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13 | description Icarus Verilog |
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14 | |
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15 | long_description Icarus Verilog is a Verilog simulation and synthesis tool. \ |
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16 | It operates as a compiler, compiling source code writen in \ |
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17 | Verilog (IEEE-1364) into some target format. For batch \ |
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18 | simulation, the compiler can generate C++ code that is \ |
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19 | compiled and linked with a run time library (called \ |
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20 | \"vvm\") then executed as a command to run the simulation. \ |
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21 | For synthesis, the compiler generates netlists in the \ |
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22 | desired format. |
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23 | |
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24 | homepage http://iverilog.icarus.com/ |
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25 | master_sites ftp://ftp.icarus.com/pub/eda/verilog/v10/ |
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26 | distname verilog-${version} |
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27 | |
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28 | checksums rmd160 77c933b712ab027b13a81e3eead7ee4f565741b7 \ |
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29 | sha256 fdaa75dfe7c58cbc471fc12710ee49b3f32fd6cc055d9181b5190cbcbbd6cada |
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30 | |
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31 | depends_lib port:bzip2 \ |
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32 | port:readline \ |
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33 | port:zlib |
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34 | |
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35 | test.run yes |
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36 | test.target check |
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37 | |
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38 | destroot.destdir prefix=${destroot}${prefix} |
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39 | |
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40 | post-destroot { |
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41 | set docdir ${destroot}${prefix}/share/doc/${name} |
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42 | xinstall -d ${docdir} |
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43 | copy ${worksrcpath}/examples ${docdir} |
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44 | xinstall -m 644 {*}[glob ${worksrcpath}/*.txt] ${docdir} |
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45 | xinstall -d ${docdir}/vvp |
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46 | xinstall -m 644 {*}[glob ${worksrcpath}/vvp/*.txt] ${docdir}/vvp |
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47 | xinstall -m 644 -W ${worksrcpath} cadpli/cadpli.txt ivlpp/ivlpp.txt \ |
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48 | ${docdir} |
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49 | } |
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50 | |
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51 | platform darwin 8 { |
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52 | depends_build-append port:bison |
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53 | } |
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54 | |
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55 | # g++-4.2: -E, -S, -save-temps and -M options are not allowed with multiple -arch flags |
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56 | universal_variant no |
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57 | |
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58 | livecheck.type regex |
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59 | livecheck.url ${master_sites} |
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60 | livecheck.regex "verilog-(\\d+(?:\\.\\d+)*)${extract.suffix}" |
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