| 1 | # $Id$ |
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| 2 | |
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| 3 | PortSystem 1.0 |
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| 4 | name veriwell |
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| 5 | version 2.8.5 |
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| 6 | categories science |
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| 7 | description VeriWell Verilog Simulator |
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| 8 | |
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| 9 | long_description \ |
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| 10 | VeriWell is a full Verilog simulator. It supports nearly all of the \ |
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| 11 | IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the \ |
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| 12 | same simulator that was sold by Wellspring Solutions in the mid-1990 \ |
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| 13 | and was included with the Thomas and Moorby book |
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| 14 | |
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| 15 | homepage http://sourceforge.net/projects/veriwell |
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| 16 | platforms darwin |
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| 17 | master_sites sourceforge |
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| 18 | checksums md5 1c1c6fb05009172d2677e34f0e511a37 |
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| 19 | distname ${name}-${version} |
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| 20 | depends_lib port:help2man |
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| 21 | |
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| 22 | # The following prevent conflicts with other Verilog simulators |
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| 23 | # that may have installed their own copies of: |
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| 24 | # acc_user.h veriuser.c veriuser.h |
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| 25 | |
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| 26 | configure.args --includedir=${prefix}/include/veriwell |
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| 27 | |
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