Opened 18 years ago

Closed 18 years ago

#10976 closed defect (fixed)

NEW: veriwell 2.8.5

Reported by: oksmith77 Owned by: yeled@…
Priority: High Milestone:
Component: ports Version:
Keywords: verilog Cc:
Port:

Description

Portfile for the Veriwell Verilog simulator.

Attachments (1)

Portfile​ (893 bytes) - added by oksmith77 18 years ago.
Portfile for Veriwell

Download all attachments as: .zip

Change History (2)

Changed 18 years ago by oksmith77

Attachment: Portfile​ added

Portfile for Veriwell

comment:1 Changed 18 years ago by markd@…

Resolution: → fixed
Status: new → closed

Committed. Thanks!

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