#10977 closed submission (fixed)
NEW: GPL Cver 2.11a Verilog Simulator
| Reported by: | oksmith77 | Owned by: | yeled@… |
|---|---|---|---|
| Priority: | High | Milestone: | |
| Component: | ports | Version: | |
| Keywords: | Verilog | Cc: | markd@… |
| Port: |
Description
Attached is an archive that contains a Portfile and patches for GPL Cver Verilog Simulator.
Attachments (1)
Change History (6)
Changed 18 years ago by oksmith77
| Attachment: | gplcver.tar.gz added |
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comment:1 Changed 18 years ago by kballard (Lily Ballard)
| Milestone: | → New Ports |
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comment:2 Changed 18 years ago by markd@…
| Cc: | markd@… added |
|---|---|
| Resolution: | → fixed |
| Status: | new → closed |
Committed. Thanks!
comment:3 Changed 17 years ago by jmpalacios (Juan Manuel Palacios)
| Milestone: | New Ports → Port Submissions |
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Milestone New Ports deleted
comment:4 Changed 16 years ago by jmroot (Joshua Root)
| Type: | enhancement → submission |
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comment:5 Changed 16 years ago by (none)
| Milestone: | Port Submissions |
|---|
Milestone Port Submissions deleted
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Archive with Portfile for GPL Cver