Ticket #19015: digi.vcd.veri

File digi.vcd.veri, 1.7 KB (added by janp@…, 16 years ago)
Line 
1$date
2        Sat Mar 28 13:32:41 2009
3$end
4$version
5        Icarus Verilog
6$end
7$timescale
8        100fs
9$end
10$scope module TestBench $end
11$var wire 1 ! netA $end
12$var wire 1 " netB $end
13$var wire 1 # netOuput $end
14$var reg 1 ! net_srcS1netA $end
15$var reg 1 " net_srcS2netB $end
16$upscope $end
17$enddefinitions $end
18#0
19$dumpvars
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23$end
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