#19015 closed defect (wontfix)
freehdl is not working (with qucs?)
Reported by: | janp@… | Owned by: | rowue@… |
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Priority: | Normal | Milestone: | |
Component: | ports | Version: | 1.7.0 |
Keywords: | Cc: | ||
Port: | freehdl |
Description
I'm not sure whether this is purely freehdl problem (suspect it is) but when a similution set up by qucs is run it runs to completion but returns no data and sends warnings.
qucs output as follows:
Output: ------- Starting new simulation on Sat 28. Mar 2009 at 09:21:40 creating netlist... done. -n running C++ conversion... done. -n compiling functions... done. -n compiling main... done. -n linking... done. simulating... -n running VCD conversion... done. Simulation ended on Sat 28. Mar 2009 at 09:21:42 Ready. Errors: ------- vcd notice, duplicate value change at t = 4000 of variable `netf' vcd notice, duplicate value change at t = 16000 of variable `netf' vcd notice, duplicate value change at t = 28000 of variable `netf' vcd notice, duplicate value change at t = 40000 of variable `netf' vcd notice, duplicate value change at t = 52000 of variable `netf' vcd notice, duplicate value change at t = 64000 of variable `netf' vcd notice, duplicate value change at t = 76000 of variable `netf' vcd notice, duplicate value change at t = 88000 of variable `netf' vcd notice, duplicate value change at t = 100000 of variable `netf' vcd notice, duplicate value change at t = 112000 of variable `netf' vcd notice, duplicate value change at t = 124000 of variable `netf' vcd notice, duplicate value change at t = 136000 of variable `netf' vcd notice, duplicate value change at t = 148000 of variable `netf' vcd notice, duplicate value change at t = 160000 of variable `netf' vcd notice, duplicate value change at t = 172000 of variable `netf' vcd notice, duplicate value change at t = 184000 of variable `netf' vcd notice, duplicate value change at t = 196000 of variable `netf'
Attachments (4)
Change History (12)
comment:1 Changed 16 years ago by rowue@…
Owner: | changed from macports-tickets@… to rowue@… |
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Status: | new → assigned |
comment:2 follow-up: 3 Changed 16 years ago by rowue@…
Changed 16 years ago by janp@…
Attachment: | Digitest.sch added |
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comment:3 Changed 16 years ago by janp@…
Replying to rowue@…:
I've tried digital (freehdl) simulation on 10.4 and 10.5 (using the BCD Project from qucs homepage). Got correct output (IMHO). If you can supply me your schematics, I would check.
I have attached a simple one. It works just fine with Verilog. BTW I have never seen freehdl work but verilog has always worked until Apple changed the way X windows works. Mind you digi.vcd is nearly twice the size when run with freehdl than with verilog. Do you need these files too?
One thing i have found particularly annoying is that qucs uses a hidden directory and Mac OS X finder doesn't (AFAIK) have provision for showing hidden files. Can get to them but it's a pain in the neck.
Changed 16 years ago by janp@…
Attachment: | Digitest.dpl added |
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comment:4 follow-up: 5 Changed 16 years ago by rowue@…
On my machine it runs freehdl - not verilog ;)
The .qucs Dir is something anoying - perhaps we should speak to Upstream about this ;)
AFAIK freehdl ist used for digital simulations in qucs.
Changed 16 years ago by janp@…
Attachment: | digi.vcd.vhdl added |
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Changed 16 years ago by janp@…
Attachment: | digi.vcd.veri added |
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comment:5 follow-up: 6 Changed 16 years ago by janp@…
Replying to rowue@…:
On my machine it runs freehdl - not verilog ;)
The .qucs Dir is something anoying - perhaps we should speak to Upstream about this ;)
AFAIK freehdl ist used for digital simulations in qucs.
On mine it runs either and I can select it in the Digital simulations properties. When I select Verilog it works fine when I select VHDL it runs to completion but qucs claims there is no Data. There is data in digi.vcd that looks OK to me I'll attach both versions. You'll know which is which from the extension.
comment:6 Changed 16 years ago by janp@…
Replying to janp@…:
I have found the problem Verilog Keeps the label in the same case freehdl changes them to lower case so if the charts had been done for verilog with uppercase it just says no data. Since I got verilog working completely first because all it needed was installation "and . /etc/profile" added. I hadn't actually checked to see what freehdl was doing there I just assumed it would be the same as I named the labels.
comment:7 Changed 16 years ago by rowue@…
Resolution: | → wontfix |
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Status: | assigned → closed |
Perhaps I should work me one time throught the documentation/manual (so I now where to change the digital simulation ;)
Since this is an upstream problem (also occuring on debian amd64) I will report to upstream (done) and won't fix it.
Thanks again - will plugin acso now.
I've tried digital (freehdl) simulation on 10.4 and 10.5 (using the BCD Project from qucs homepage). Got correct output (IMHO). If you can supply me your schematics, I would check.