Ticket #19015: digi.vcd.vhdl

File digi.vcd.vhdl, 3.2 KB (added by janp@…, 16 years ago)
Line 
1$date
2     Jan 16 2008  19:37:19
3$end
4$version
5    FREEHDL 0.0.4
6$end
7$timescale
8    1 ps
9$end
10$scope module arch_testbench $end
11$var   trireg 1 ! neta $end
12$var   trireg 1 " netb $end
13$var   trireg 1 # netouput $end
14$scope module s1 $end
15$var   trireg 1 $ s1-_implicit_wait_for $end
16$upscope $end
17$scope module s2 $end
18$var   trireg 1 % s2-_implicit_wait_for $end
19$upscope $end
20$upscope $end
21$enddefinitions $end
22#0
23$dumpvars
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29$end
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