UPDATE: GPL Cver 2.12a Verilog Simulator
| Reported by: |
oksmith77 |
Owned by: |
nox@… |
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Priority:
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High
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Milestone:
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Component:
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ports
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Version:
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Keywords:
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Cc:
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Port:
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Attached is an archive that contains a Portfile and patches for the latest version of GPL Cver Verilog Simulator.
The old version of the portfile does not appear to work because the old source code no longer appears to be on the host site.
Change History (7)
| Priority: |
Important →
High
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| Version: |
1.4.40
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| Owner: |
changed from markd@… to nox@…
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| Resolution: |
→ fixed
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| Status: |
assigned →
closed
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| Type: |
enhancement →
update
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Archive with Portfile for GPL Cver 2.12a Verilog Simulator